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ICS9LPRS365
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64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
Recommended Application: CK505 compliant clock with fully integrated voltage regulator and Internal series resistor on differential outputs Output Features: * 2 - CPU differential low power push-pull pairs * 9 - SRC differential low power push-pull pairs * 1 - CPU/SRC selectable differential low power push-pull pair * 1 - SRC/DOT selectable differential low power push-pull pair * 5 - PCI, 33MHz * 1 - PCI_F, 33MHz free running * 1 - USB, 48MHz * 1 - REF, 14.318MHz Key Specifications: * CPU outputs cycle-cycle jitter < 85ps * SRC output cycle-cycle jitter < 125ps * PCI outputs cycle-cycle jitter < 250ps * +/- 100ppm frequency accuracy on CPU & SRC clocks Features/Benefits: * Does not require external pass transistor for voltage regulator * Integrated series resistors on differential outputs, Zo=50 * Supports spread spectrum modulation, default is 0.5% down spread * Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning * Selectable between one SRC differential push-pull pair and two single-ended outputs
PCI0/CR#_A VDDPCI PCI1/CR#_B PCI2/TME PCI3 PCI4/27_Select PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO SRCT0/DOTT_96 SRCC0/DOTC_96 GND VDDPLL3 27MHz_NonSS/SRCT1/SE1 27MHz_SS/SRCC1/SE2 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC SRCT3/CR#_C SRCC3/CR#_D VDDSRC_IO SRCT4 SRCC4 GNDSRC SRCT9 SRCC9 SRCC11/CR#_G
Pin Define
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK SDATA REF0/FSLC/TEST_SEL VDDREF X1 X2 GNDREF FSLB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0 CPUC0 GNDCPU CPUT1_F CPUC1_F VDDCPU_IO NC CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 VDDSRC_IO SRCT7/CR#_F SRCC7/CR#_E GNDSRC SRCT6 SRCC6 VDDSRC PCI_STOP# CPU_STOP# VDDSRC_IO SRCC10 SRCT10 SRCT11/CR#_H
Top View
9LPRS365
64-TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor
Table 1: CPU Frequency Select Table FS LC B0b7 0 0 0 0 1 1 1 1
2
FSLB B0b6 0 0 1 1 0 0 1 1
1
FS LA B0b5 0 1 0 1 0 1 0 1
1
CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00
SRC MHz
PCI MHz
REF MHz
USB MHz
DOT MHz
100.00
33.33
14.318
48.00
96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.
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Pin Description
PIN # PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output. 3.3V PCI clock output / 27MH mode select for pin17, 18 strap. On powerup, the logic value on this pin determines the power-up default of DOT_96/SRC0 and 27MHz/SRC1 output and the function talbe for the pin17 and pin18. Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground for PCI clocks. Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Ground pin for the 48MHz outputs. 1.05V to 3.3V from external power supply True clock of SRC or DOT96. The power-up default function depends on 27_Select,1= SRC0 0=DOT96 True clock of SRC or DOT96. The power-up default function depends on 27_Select,1= SRC0 0=DOT96 Ground pin for the DOT96 clocks. Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
1
PCI0/CR#_A
I/O
2
VDDPCI
PWR
3
PCI1/CR#_B
I/O
4
PCI2/TME
I/O
5 6
PCI3 PCI4/27_Select
OUT I/O
7
PCI_F5/ITP_EN
I/O
8 9 10 11 12 13 14 15 16
GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 DOTC_96/SRCC0 GND VDD
PWR PWR I/O PWR PWR OUT OUT PWR PWR
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Pin Description (Continued)
PIN # 17 PIN NAME 27MHz_NonSS/SRCT1/SE1 TYPE OUT DESCRIPTION True clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determins the power-up default, 1=27MHz non-spread SE clock, 0 = LCD_SST 100MHz differential clock. True clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determins the power-up default, 1=27MHz spread SE clock, 0 = LCD_SSC 100MHz differential clock. Ground pin for SRC / SE1 and SE2 clocks, PLL3. 1.05V to 3.3V from external power supply True clock of differential SRC/SATA clock pair. Complement clock of differential SRC/SATA clock pair. Ground pin for SRC clocks. True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default), 1= CR#_D controls SRC4 pair 1.05V to 3.3V from external power supply True clock of differential SRC clock pair 4 Complement clock of differential SRC clock pair 4 Ground pin for SRC clocks. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. SRC11 complement /Clock Request control for SRC9 pair The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9
18 19 20 21 22 23
27MHz_SS/SRCC1/SE2 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC
OUT PWR PWR OUT OUT PWR
24
SRCT3/CR#_C
I/O
25
SRCC3/CR#_D
I/O
26 27 28 29 30 31
VDDSRC_IO SRCT4 SRCC4 GNDSRC SRCT9 SRCC9
PWR I/O I/O PWR OUT OUT
32
SRCC11/CR#_G
I/O
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Pin Description (Continued)
PIN # PIN NAME TYPE DESCRIPTION SRC11 true or Clock Request control H for SRC10 pair The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3, bit 6 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10. True clock of differential SRC clock pair. Cpmplement clock of differential SRC clock pair. 1.05V to 3.3V from external power supply Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values VDD pin for SRC Pre-drivers, 3.3V nominal Complement clock of low power differential SRC clock pair. True clock of low power differential SRC clock pair. Ground for SRC clocks SRC7 complement or Clock Request control E for SRC6 pair The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_E controls SRC6. SRC7 true or Clock Request control 8 for SRC8 pair The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space Byte 6, bit 6 0 = SRC7# enabled (default) 1 = CR#_F controls SRC8. 1.05V to 3.3V from external power supply Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8# 1 = ITP# True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8 1 = ITP No Connect
33
SRCT11/CR#_H
I/O
34 35 36 37 38 39 40 41 42
SRCT10 SRCC10 VDDSRC_IO CPU_STOP# PCI_STOP# VDDSRC SRCC6 SRCT6 GNDSRC
OUT OUT PWR IN IN PWR OUT OUT PWR
43
SRCC7/CR#_E
I/O
44
SRCT7/CR#_F
I/O
45
VDDSRC_IO
PWR
46
CPUC2_ITP/SRCC8
OUT
47
CPUT2_ITP/SRCT8
OUT
48
NC
N/A
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Pin Description (Continued)
PIN # 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PIN NAME VDDCPU_IO CPUC1_F CPUT1_F GNDCPU CPUC0 CPUT0 VDDCPU CK_PWRGD/PD# FSLB/TEST_MODE GNDREF X2 X1 VDDREF REF0/FSLC/TEST_SEL SDATA SCLK TYPE PWR OUT OUT PWR OUT OUT PWR IN IN PWR OUT IN PWR I/O I/O IN DESCRIPTION 1.05V to 3.3V from external power supply Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT. True clock of low power differential CPU clock pair. This clock will be free-running during iAMT. Ground Pin for CPU Outputs Complement clock of low power differential CPU clock pair. True clock of low power differential CPU clock pair. Power Supply 3.3V nominal. Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. Ground pin for crystal oscillator circuit Crystal output, nominally 14.318MHz. Crystal input, Nominally 14.318MHz. Power pin for the REF outputs, 3.3V nominal. 3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification Table. Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant.
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Pin Configuration
CPUC2_ITP/SRCC8
FSLB/TEST_MODE
CPUT2_ITP/SRCT8
CK_PWRGD/PD#
SRCC7/CR#_E
SRCT7/CR#_F
VDDCPU_IO
VDDSRC_IO
CPUC1_F
CPUT1_F
GNDCPU
64 63 62 GNDREF X2 X1 VDDREF REF0/FSLC/TEST_SEL SDATA 1 2 3 4 5 6
61
60 59 58
57
56 55 54
53
52 51 50
49 48 SRCT6 47 SRCC6 46 VDDSRC 45 PCI_STOP# 44 CPU_STOP# 43 VDDSRC_IO
SCLK 7 PCI0/CR#_A 8 VDDPCI 9 PCI1/CR#_B 10 PCI2/TME 11 PCI3 12 PCI4/27_Select 13 PCI_F5/ITP_EN 14 GNDPCI 15 VDD48 16 17 18 19 VDD96_IO GND48 USB_48MHz/FSLA 20 SRCT0/DOTT_96
GNDSRC 42 SRCC10 41 SRCT10 40 SRCT11/CR#_H 39 SRCC11/CR#_G 38 SRCC9 37 SRCT9 36 GNDSRC 35 SRCC4 34 SRCT4 33 VDDSRC_IO 32 SRCC3/CR#_D
VDDCPU
CPUC0
CPUT0
9LPRS365
21 22 23 GND SRCC0/DOTC_96 VDDPLL3
24 27MHz_NonSS/SRCT1/SE1
25 26 27 GND 27MHz_SS/SRCC1/SE2 VDDPLL3_IO
NC
28 SRCT2/SATAT
29 30 31 SRCC2/SATAC GNDSRC SRCT3/CR#_C
64-pin MLF
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Pin Description
PIN #
1 2 3 4 5 6 7
GNDREF X2 X1 VDDREF REF0/FSLC/TEST_SEL SDATA SCLK
PIN NAME
TYPE
PWR OUT IN PWR I/O I/O IN
DESCRIPTION
Ground pin for crystal oscillator circuit Crystal output, nominally 14.318MHz. Crystal input, Nominally 14.318MHz. Power pin for the REF outputs, 3.3V nominal. 3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification Table. Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output. 3.3V PCI clock output / 27MH mode select for pin17, 18 strap. On powerup, the logic value on this pin determines the power-up default of DOT_96/SRC0 and 27MHz/SRC1 output and the function talbe for the pin17 and pin18. Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground for PCI clocks. Power supply for USB clock, nominal 3.3V.
8
PCI0/CR#_A
I/O
9
VDDPCI
PWR
10
PCI1/CR#_B
I/O
11
PCI2/TME
I/O
12 13
PCI3 PCI4/27_Select
OUT I/O
14
PCI_F5/ITP_EN
I/O
15 16
GNDPCI VDD48
PWR PWR
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Pin Description (Continued)
PIN #
17 18 19 20 PIN NAME
USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0
TYPE
I/O PWR PWR OUT
DESCRIPTION
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Ground pin for the 48MHz outputs.
1.05V to 3.3V from external power supply
True clock of SRC or DOT96. The power-up default function depends on 27_Select,1= SRC0 0=DOT96 True clock of SRC or DOT96. The power-up default function depends on 27_Select,1= SRC0 0=DOT96 Ground pin for the DOT96 clocks. Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. True clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determins the power-up default, 1=27MHz non-spread SE clock, 0 = LCD_SST 100MHz differential clock. True clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determins the power-up default, 1=27MHz spread SE clock, 0 = LCD_SSC 100MHz differential clock. Ground pin for SRC / SE1 and SE2 clocks, PLL3.
21 22 23 24 25 26 27 28 29 30
DOTC_96/SRCC0 GND VDD
OUT PWR PWR OUT OUT PWR PWR OUT OUT PWR
27MHz_NonSS/SRCT1/SE1 27MHz_SS/SRCC1/SE2
GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC
1.05V to 3.3V from external power supply
True clock of differential SRC/SATA clock pair. Complement clock of differential SRC/SATA clock pair. Ground pin for SRC clocks. True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default), 1= CR#_D controls SRC4 pair
31
SRCT3/CR#_C
I/O
32
SRCC3/CR#_D
I/O
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Pin Description (Continued)
PIN #
33 34 35 36 37 38 PIN NAME
VDDSRC_IO SRCT4 SRCC4 GNDSRC SRCT9 SRCC9
TYPE
PWR I/O I/O PWR OUT OUT
DESCRIPTION 1.05V to 3.3V from external power supply
True clock of differential SRC clock pair 4 Complement clock of differential SRC clock pair 4 Ground pin for SRC clocks. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. SRC11 complement /Clock Request control for SRC9 pair The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9 SRC11 true or Clock Request control H for SRC10 pair The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3, bit 6 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10. True clock of differential SRC clock pair. Cpmplement clock of differential SRC clock pair.
39
SRCC11/CR#_G
I/O
40
SRCT11/CR#_H
I/O
41 42 43 44 45 46 47 48
SRCT10 SRCC10 VDDSRC_IO CPU_STOP# PCI_STOP# VDDSRC SRCC6 SRCT6
OUT OUT PWR IN IN PWR OUT OUT
1.05V to 3.3V from external power supply
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values VDD pin for SRC Pre-drivers, 3.3V nominal Complement clock of low power differential SRC clock pair. True clock of low power differential SRC clock pair.
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Pin Description (Continued)
PIN #
49
GNDSRC
PIN NAME
TYPE
PWR
DESCRIPTION
Ground for SRC clocks SRC7 complement or Clock Request control E for SRC6 pair The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_E controls SRC6. SRC7 true or Clock Request control 8 for SRC8 pair The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space Byte 6, bit 6 0 = SRC7# enabled (default) 1 = CR#_F controls SRC8.
50
SRCC7/CR#_E
I/O
51
SRCT7/CR#_F
I/O
52
VDDSRC_IO
PWR
1.05V to 3.3V from external power supply
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8# 1 = ITP# True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8 1 = ITP No Connect
53
CPUC2_ITP/SRCC8
OUT
54
CPUT2_ITP/SRCT8
OUT
55 56 57 58 59 60 61 62 63 64
NC VDDCPU_IO CPUC1_F CPUT1_F GNDCPU CPUC0 CPUT0 VDDCPU CK_PWRGD/PD# FSLB/TEST_MODE
N/A PWR OUT OUT PWR OUT OUT PWR IN IN
1.05V to 3.3V from external power supply
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT. True clock of low power differential CPU clock pair. This clock will be free-running during iAMT. Ground Pin for CPU Outputs Complement clock of low power differential CPU clock pair. True clock of low power differential CPU clock pair. Power Supply 3.3V nominal. Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.
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ICS9LPRS365
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General Description
ICS9LPRS365 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS9LPRS365 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support.
Block Diagram
X1 R EF X2
REF CPU(1:0)
OSC
SRC8/CPU_ITP
CPU
CPU PLL1 SS
SRC
SR C _M A IN
SRC(11-9,4:3, 7:6)
PCI33MHz SRC PCIF5 (4:0)
PLL3 SS
PCI33MHz
SRC2/SATA FSLA CKPWRGD/PD# PCI_STOP# CPU_STOP# CR#_(A:H) 27_Select TME, ITP_EN FSLC/TESTSEL FSLB/TESTMODE 27MHz/SRC1/SE(2:1)
Control Logic
Differential Output
SE Outputs
7
27MHz_NonSS
SRC0/DOT96
PLL2 Non-SS
SATA DOT96MHz 48MHz 48MHz
Power Groups
Pin Number VDD GND 49 52 55 52 26, 36, 45 23, 29, 42 39 23, 29, 42 20 19 16 19 12 11 9 11 61 58 2 8
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Description CPUCLK Low power outputs Master Clock, Analog Low power outputs SRCCLK PLL 1 Low power outputs PLL3/SE PLL 3 DOT 96Mhz Low power outputs USB 48 Xtal, REF PCICLK
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Absolute Maximum Ratings
PARAMETER Maximum Supply Voltage Maximum Supply Voltage Maximum Input Voltage Minimum Input Voltage Storage Temperature Input ESD protection SYMBOL VDDxxx VDDxxx_IO VIH VIL Ts ESD prot CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply 3.3V LVCMOS Inputs Any Input Human Body Model GND - 0.5 -65 2000 150 MIN MAX 4.6 3.8 4.6 UNITS V V V V
Notes 1,7 1,7 1,7,8 1,7 1,7 1,7
C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER Ambient Operating Temp Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Low Threshold InputHigh Voltage (Test Mode) Low Threshold InputHigh Voltage Low Threshold InputLow Voltage SYMBOL Tambient VDDxxx VDDxxx_IO VIHSE VILSE IIN IINRES VOHSE VOLSE VOHDIF VOLDIF VIH_FS_TEST VIH_FS VIL_FS IDD_DEFAULT IDD_PLL3DIF Operating Supply Current IDD_PLL3SE IDD_IO IDD_PD3.3 Power Down Current IDD_PDIO IDD_iAMT3.3 IDD_iAMT0.8 Fi Lpin CIN Input Capacitance Spread Spectrum Modulation Frequency
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CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply Single-ended inputs Single-ended inputs VIN = VDD , VIN = GND Inputs with pull or pull down resistors VIN = VDD , VIN = GND Single-ended outputs, IOH = -1mA Single-ended outputs, IOL = 1 mA Differential Outputs, IOH = TBD mA Differential Outputs, IOL = TBD mA 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% 3.3V supply, PLL3 off 3.3V supply, PLL3 Differential Out 3.3V supply, PLL3 Single-ended Out 0.8V supply, Differential IO current, all outputs enabled 3.3V supply, Power Down Mode 0.8V IO supply, Power Down Mode 3.3V supply, iAMT Mode 0.8V IO supply, iAMTMode VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins Triangular Modulation
MIN 0 3.135 1 2 VSS - 0.3 -5 -200 2.4
TYPICAL
MAX 70 3.465 3.465 VDD + 0.3 0.8 5 200
UNITS C V V V V uA uA V
Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1
0.4 0.7 0.9 0.4 2 0.7 VSS - 0.3 95 106 101 25 32 31 0.23 113 31 VDD + 0.3 1.5 0.35 250 250 250 80 1 0.1 TBD 0.8 14.318 7 1.5 5 6 5 30 33
V V V V V V mA mA mA mA mA mA mA mA MHz nH pF pF pF kHz
iAMT Mode Current Input Frequency Pin Inductance
COUT CINX fSSMOD
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ICS9LPRS365
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AC Electrical Characteristics - Input/Common Parameters
PARAMETER Clk Stabilization Tdrive_SRC Tdrive_PD# Tdrive_CPU Tfall_PD# Trise_PD# SYMBOL TSTAB TDRSRC TDRPD TDRSRC T FALL T RISE CONDITIONS From VDD Power-Up or deassertion of PD# to 1st clock SRC output enable after PCI_STOP# de-assertion Differential output enable after PD# de-assertion CPU output enable after CPU_STOP# de-assertion Fall/rise time of PD#, PCI_STOP# and CPU_STOP# inputs MIN MAX 1.8 15 300 10 5 5 UNITS ms ns us ns ns ns Notes 1 1 1 1 1 1
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Maximum Output Voltage Minimum Output Voltage Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Duty Cycle CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle CPU[1:0] Skew CPU[2_ITP:0] Skew SRC[10:0] Skew SYMBOL tSLR tFLR tSLVAR VHIGH VLOW VSWING VXABS VXABSVAR DCYC CPUJ C2C SRCJ C2C DOTJ C2C CPUSKEW10 CPUSKEW20 SRCSKEW CONDITIONS Differential Measurement Differential Measurement Single-ended Measurement Includes overshoot Includes undershoot Differential Measurement Single-ended Measurement Single-ended Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement 45 -300 300 300 550 140 55 85 125 250 100 150 TBD MIN 2.5 2.5 MAX 8 8 20 1150 UNITS V/ns V/ns % mV mV mV mV mV % ps ps ps ps ps ps NOTES 1,2 1,2 1 1 1 1 1,3,4 1,3,5 1 1 1 1 1 1 1
Electrical Characteristics - 27MHz_Spread / 27MHz_NonSpread
PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Rise Time Fall Time Duty Cycle Jitter SYMBOL ppm T period VOH VOL IOH IOL ts lewr/f tr1 tf1 dt1 tltj tjpk-pk tjc yc-cy c
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CONDITIONS see Tperiod min-max values 27.000MHz output nominal IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V Long Term (10us)
MIN -50 -15 37.0365 2.4
TYP
MAX 50 15 37.0376
UNITS ppm
Notes 1,2 1,2,3 1 1 1 1 1 1 1 1 1 1 1 1 1
V 0.55 V mA -23 mA mA 27 mA V/ns ns ns % ps ps ps 4 2 2 55 800 200 200
-29 29 1 0.5 0.5 45 -200
VT = 1.5 V
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ICS9LPRS365
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Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Skew Intentional PCI-PCI delay Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tskew tdelay tjcyc-cyc CONDITIONS see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread 33.33MHz output nominal/spread IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 1 1 45 30 38 4 4 55 250 200 nominal 500 -33 -33 MIN -300 29.99100 29.49100 2.4 0.4 MAX 300 30.00900 30.15980 30.65980 UNITS ppm ns ns ns V V mA mA mA mA V/ns V/ns % ps ps ps NOTES 1,6 6 6 6 1 1 1 1 1 1 1 1 1 1 1,9 1
Intentional PCI Clock to Clock Delay
200 ps nominal steps
PCI0 PCI1 PCI2 PCI3 PCI4 PCI_F5
1.0ns
Electrical Characteristics - USB48MHz
PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle
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SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tjcyc-cyc
CONDITIONS see Tperiod min-max values 48.00MHz output nominal 48.00MHz output nominal IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V
MIN -100 20.83125 20.48130 2.4
MAX 100 20.83542 21.18540 0.4
UNITS ppm ns ns V V mA mA mA mA V/ns V/ns % ps
NOTES 1,2 2 2 1 1 1 1 1 1 1 1 1 1
-29 -23 29 27 1 1 45 2 2 55 350
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ICS9LPRS365
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Electrical Characteristics - SMBus Interface
PARAMETER SMBus Voltage Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency SYMBOL VDD VOLSMB IPULLUP T RI2C T FI2C F SMBUS @ IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Block Mode 4 1000 300 100 CONDITIONS MIN 2.7 MAX 5.5 0.4 UNITS V V mA ns ns kHz Notes 1 1 1 1 1 1
Electrical Characteristics - REF-14.318MHz
PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V -33 30 1 1 45 MIN -300 69.8203 69.8203 2.4 0.4 -33 38 4 4 55 1000 MAX 300 69.8622 70.86224 UNITS ppm ns ns V V mA mA V/ns V/ns % ps Notes 1,2 2 2 1 1 1 1 1 1 1 1
Notes on Electrical Characteristics:
1 2 3 4 5
Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing centered around differential zero Vxabs is defined as the voltage where CLK = CLK#
Only applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
6 7 8 9
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz Operation under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD See PCI Clock-to-Clock Delay Figure
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ICS9LPRS365
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Table 1: CPU Frequency Select Table FSLC B0b7 0 0 0 0 1 1 1 1
2
FSLB B0b6 0 0 1 1 0 0 1 1
1
FS LA B0b5 0 1 0 1 0 1 0 1
1
CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00
SRC MHz
PCI MHz
REF MHz
USB MHz
DOT MHz
100.00
33.33
14.318
48.00
96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 2: pin17, 18 Configuration 27_Select 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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B1b4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B1b3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
B1b2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
B1b1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Pin 17
MHz 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 24.576 98.304 27.000 25.000 N/A N/A N/A N/A
Pin 18
MHz 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 98.304 98.304 27.000 25.000 N/A N/A N/A N/A
Spread % PLL 3 disabled -0.50% -1% -1.50% (+/-0.25) (+/-0.5) N/A None None None None None N/A N/A N/A N/A
Comment
SRCCLK1 from SRC_MAIN Only SRCCLK1 from PLL3 Only SRCCLK1 from PLL3 Only SRCCLK1 from PLL3 Only SRCCLK1 from PLL3 Only SRCCLK1 from PLL3 N/A 24.576Mhz on SE1 and SE2 24.576Mhz on SE1, 98.304Mhz on SE2 98.304Mhz on SE1 and SE2 27Mhz on SE1 and SE2 25Mhz on SE1 and SE2 N/A N/A N/A
27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS
N/A N/A N/A N/A N/A
27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS
N/A N/A N/A N/A N/A
-0.5%
-1% -1.5% -2% -0.75% -1.25%
-1.75%
+-0.5% +-0.75%
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ICS9LPRS365
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Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout 0.3V 0 0 0 0.4V 0 0 1 0.5V 0 1 0 0.6V 0 1 1 0.7V 1 0 0 0.8V 1 0 1 0.9V 1 1 0 1.0V 1 1 1
CPU Power Management Table
PD# CPU_STOP# 1 0 1 1 1 X 0 X PCI_STOP# 1 X X X M1 CR# X X X X SMBus Register OE Enable Enable Enable Disable CPU1 Running Low/20K High Low/20K Running CPU1# Running Low Low Low Running CPU(0,2) Running Low/20K High Low/20K Low/20K CPU(0,2)# Running Low Low Low Low
SRC, LCD, DOT Power Management Table
PD# CPU_STOP# 1 0 1 1 1 X X X X X PCI_STOP# 1 X 0 X X M1 CR# 0 X X 1 X SMBus Register OE Enable Enable Enable Enable Disable SRC/LCD SRC#/LCD# Free-Run Running Low/20K Running Running Low/20K Low/20K Running Low Running Running Low Low SRC/LCD SRC#/LCD# PCI Stoppable/CR Selected Running Running Low/20K High Low/20K Low/20K Low/20K Low Low Low Low Low DOT Running Low/20K Running Running Low/20K Low/20K DOT# Running Low Running Running Low Low
Singled-ended Power Management Table
PD# CPU_STOP# 1 0 1 1 X X X X PCI_STOP# 1 X 0 X M1 CR# X X X X SMBus Register OE Enable Enable Enable Disable PCIF/PCI Free-run Running Low Running Low Low PCIF/PCI Stoppable Running Low Low Low Low USB Running Low Running Low Low REF Running Low Running Low Low
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ICS9LPRS365
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General SMBus serial interface information for the ICS9LPRS365 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
ACK
Byte N + X - 1 N P Not acknowledge stoP bit
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Byte 0 FS Readback and PLL Selection Register
Bit 7 6 5 4 3 2 1 0 Pin Name FSLC FSLB FSLA iAMT_EN Reserved SRC_Main_SEL SATA_SEL PD_Restore Description CPU Freq. Sel. Bit (Most Significant) CPU Freq. Sel. Bit CPU Freq. Sel. Bit (Least Significant) Set via SMBus or dynamically by CK505 if detects dynamic M1 Reserved Select source for SRC Main Select source for SATA clock If config saved, on deassert return to last known state else clear all config as if cold power on and go to latches open state Type 0 1 Default Latch R See Table 1 : CPU Frequency Select Latch R Table Latch R R RW RW RW RW SRC Main = PLL1 SATA = SRC_Main Configuration Not Saved SRC Main = PLL3 SATA = PLL2 Configuration Saved Legacy Mode iAMT Enabled 0 0 0 0 1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit 7 6 5 4 3 2 1 0 Pin 13/14 17/18 Name SRC0_SEL PLL1_SSC_SEL Reserved PLL3_CF3 PLL3_CF2 PLL3_CF1 PLL3_CF0 PCI_SEL Description Select SRC0 or DOT96 Select 0.5% down or center SSC PLL3 Quick PLL3 Quick PLL3 Quick PLL3 Quick Config Bit Config Bit Config Bit Config Bit 3 2 1 0 Type RW RW RW RW RW RW RW RW Default Note 1 0 0 0 See Table 2: pin17, 18 Configuration 0 Only applies if Byte 0, bit 2 = 0. 1 0 PCI from PCI from PLL1 1 SRC_MAIN 0 SRC0 Down spread 1 DOT96 Center spread
PCI_SEL
Note 1 : When 27_Select pin = 0, B1b7 PWO = 1, , when 27_Select pin = 1, PWO = 0
Byte 2 Output Enable Register
Bit 7 6 5 4 3 2 1 0 Pin Name REF_OE USB_OE PCIF5_OE PCI4_OE PCI3_OE PCI2_OE PCI1_OE PCI0_OE Description Output enable for REF, if disabled output is tristated Output enable for USB Output enable for PCI5 Output enable for PCI4 Output enable for PCI3 Output enable for PCI2 Output enable for PCI1 Output enable for PCI0 Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Output Output Output Output Output Output Disabled Disabled Disabled Disabled Disabled Disabled Disabled 1 Output Enabled Output Output Output Output Output Output Output Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1
Byte 3 Output Enable Register
Bit 7 6 5 4 3 2 1 0 Pin Name SRC11_OE SRC10_OE SRC9_OE SRC8/ITP_OE SRC7_OE SRC6_OE Reserved SRC4_OE Description Output enable for SRC11 Output enable for SRC10 Output enable for SRC9 Output enable for SRC8 or ITP Output enable for SRC7 Output enable for SRC6 Reserved Output enable for SRC4 Type RW RW RW RW RW RW RW RW Output Output Output Output Output Output Output Output 0 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Output Output Output Output Output Output Output Output 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1
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Byte 4 Output Enable and Spread Spectrum Disable Register
Bit 7 6 5 4 3 2 1 0 Pin Name SRC3_OE SATA/SRC2_OE SRC1_OE SRC0/DOT96_OE CPU1_OE CPU0_OE PLL1_SSC_ON PLL3_SSC_ON Description Output enable for SRC3 Output enable for SATA/SRC2 Output enable for SRC1 Output enable for SRC0/DOT96 Output enable for CPU1 Output enable for CPU0 Enable PLL1's spread modulation Enable PLL3's spread modulation Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Spread Disabled Spread Disabled 1 Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Spread Enabled Spread Enabled Default 1 1 1 1 1 1 1 1
Byte 5 Clock Request Enable/Configuration Register
Bit 7 6 5 4 3 2 1 0 Pin Name CR#_A_EN CR#_A_SEL CR#_B_EN CR#_B_SEL CR#_C_EN CR#_C_SEL CR#_D_EN CR#_D_SEL Description Enable CR#_A (clk req), PCI0_OE must be = 1 for this bit to take effect Sets CR#_A to control either SRC0 or SRC2 Enable CR#_B (clk req) Sets CR#_B -> SRC1 or SRC4 Enable CR#_C (clk req) Sets CR#_C -> SRC0 or SRC2 Enable CR#_D (clk req) Sets CR#_D -> SRC1 or SRC4 Type RW RW RW RW RW RW RW RW 0 Disable CR#_A CR#_A -> SRC0 Disable CR#_B CR#_B -> SRC1 Disable CR#_C CR#_C -> SRC0 Disable CR#_D CR#_D -> SRC1 1 Enable CR#_A CR#_A -> SRC2 Enable CR#_B CR#_B -> SRC4 Enable CR#_C CR#_C -> SRC2 Enable CR#_D CR#_D -> SRC4 Default 0 0 0 0 0 0 0 0
Byte 6 Clock Request Enable/Configuration and Stop Control Register
Bit 7 6 5 4 3 2 1 Pin Name CR#_E_EN CR#_F_EN CR#_G_EN CR#_H_EN Reserved Reserved SSCD_STP_CRTL Description Enable CR#_E (clk req) -> SRC6 Enable CR#_F (clk req) -> SRC8 Enable CR#_G (clk req) -> SRC9 Enable CR#_H (clk req) -> SRC10 Reserved Reserved If set, LCD_SS stops with PCI_STOP# Type RW RW RW RW RW RW RW 0 Disable CR#_E Disable CR#_F Disable CR#_G Disable CR#_H 1 Enable CR#_E Enable CR#_F Enable CR#_G Enable CR#_H Default 0 0 0 0 0 0 0
Free Running
0
SRC_STP_CRTL
If set, SRCs stop with PCI_STOP#
RW
Free Running
Stops with PCI_STOP# assertion Stops with PCI_STOP# assertion
0
Byte 7 Vendor ID/ Revision ID
Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit 3 Rev Code Bit 2 Rev Code Bit 1 Rev Code Bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 Description Revision ID Type R R R R R R R R 0 1 Default X X X X 0 0 0 1
Vendor specific
Vendor ID ICS is 0001, binary
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Byte 8 Device ID and Output Enable Register
Bit 7 6 5 4 3 2 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved Description Table of Device identifier codes, used for differentiating between CK505 package options, etc. Reserved Reserved Type R R R R RW RW 0 1 Default 1 1 0 1 0 0 27_Sel ect power on latch 27_Sel ect power on latch
See Device ID Table -
1 SE1_OE Output enable for SE1 RW Disabled Enabled
0 SE2_OE Output enable for SE2 RW Disabled Enabled
Byte 9 Output Control Register
Bit 7 6 5 4 3 2 1 0 Pin Name PCIF5 STOP EN TME_Readback REF Strength Test Mode Select Description Allows control of PCIF5 with assertion of PCI_STOP# Truested Mode Enable (TME) strap status Sets the REF output drive strength Allows test select, ignores REF/FSC/TestSel Type RW R RW RW RW RW RW RW 0 Free running normal operation 1X (2Loads) Outputs HI-Z Normal operation 1 Default Stops with PCI_STOP# 0 assertion no overclocking 0 2X (3 Loads) 1 Outputs = REF/N 0 Test mode 0 1 0 1
Test Mode Entry Allows entry into test mode, ignores FSB/TestMode IO_VOUT2 IO_VOUT1 IO_VOUT0 IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit)
See Table 3: V_IO Selection (Default is 0.8V)
Byte 10 Reserved Register
Bit 7 6 5 4 3 2 1 0 Pin Name 27_Selec Latch read back Reserved Reserved Reserved Reserved Reserved CPU 1 Stop Enable CPU 0 Stop Enable Description Readback of 27_Select latch Type R RW RW RW RW RW RW RW 0 Dot96/ LCD_SS /SE 1 SRC0/ 27MHz Default 27_Sel ect latch 1 1 1 1 1 1 1
Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP#
Free Running Free Running
Stoppable Stoppable
Byte 11 Clock Strength Control
Bit 7 6 5 4 3 2 1 0 Pin Name 48MHz PCIF5 PCI4 PCI3 PCI2 PCI1 PCI0 Reserved Description Type RW RW RW RW RW RW RW RW 0 1x 1x 1x 1x 1x 1x 1x 1 2x 2x 2x 2x 2x 2x 2x Default 0 0 0 0 0 0 0 0
Strength control
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ICS9LPRS365
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Byte 12 Byte Count Register
Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Description Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 1 1 0 1
Read Back byte count register, max bytes = 32
Byte 13 VCO Frequency Control Register PLL1
Bit 7 6 5 4 3 2 1 0 Pin Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Description N Divider 8 N Divider 9 The decimal representation of M Div (5:0) + 2 is equal to reference divider value. Default at power up = latch-in or Byte 0 Rom table. Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X
Byte 14 VCO Frequency Control Register PLL1
Bit 7 6 5 4 3 2 1 0 Pin Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Description Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X
The decimal representation of N Div (9:0) +8 is equal to VCO divider value. Default at power up = latch-in or Byte 0 Rom table.
Byte 15 Spread Spectrum Control Register PLL1
Bit 7 6 5 4 3 2 1 0 Pin Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Description Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X
These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values.
1218--07/11/06
22
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ICS9LPRS365
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Byte 16 Spread Spectrum Control Register PLL1
Bit 7 6 5 4 3 2 1 0 Pin Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Description Reserved Type RW RW RW RW RW RW RW RW 0 1 Default 0 x X X X X X X
These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values.
Byte 17 VCO Frequency Control Register PLL3
Bit 7 6 5 4 3 2 1 0 Pin Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Description N Divider 8 N Divider 9 The decimal representation of M Div (5:0) + 2 is equal to reference divider value. Default at power up = latch-in or Byte 0 Rom table. Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X
Byte 18 VCO Frequency Control Register PLL3
Bit 7 6 5 4 3 2 1 0 Pin Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Description Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X
The decimal representation of N Div (9:0) +8 is equal to VCO divider value. Default at power up = latch-in or Byte 0 Rom table.
Byte 19 Spread Spectrum Control Register PLL3
Bit 7 6 5 4 3 2 1 0 Pin Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Description Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X
These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values.
Byte 20 Spread Spectrum Control Register PLL3
Bit 7 6 5 4 3 2 1 0 Pin Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Description Reserved Type RW RW RW RW RW RW RW RW 0 1 Default 0 x X X X X X X
These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values.
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ICS9LPRS365
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Systems, Inc.
Test Clarification Table
Comments
FSLC/ TEST_SEL HW PIN
HW
SW
REF/N or HI-Z B9b4
FSLB/ TEST TEST_MODE ENTRY BIT HW PIN B9b3
Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ V<2.0V then use FSLC FSLB/TEST_MODE -->low Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control
<2.0V >2.0V >2.0V >2.0V
X 0 0 1
0 X X X
0 0 1 0
OUTPUT NORMAL HI-Z REF/N REF/N
>2.0V
1
X
1
REF/N
<2.0V
X
1
0
HI-Z
<2.0V
X
1
1
REF/N
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B9b4: 1= REF/N, Default = 0 (HI-Z)
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ICS9LPRS365
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Dimension
P64
N
P33
c
L
SYMBOL A A1 A2 b c D E E1 e L N aaa VARIATIONS
Top View
INDEX AREA E1 E
12 D
P32
a
6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0 8 0 8 -0.10 -.004
A2 A1
A
-Ce
b SEATING PLANE
N 64
D mm. MIN 16.90 MAX 17.10 MIN .665
D (inch) MAX .673
Reference Doc.: JEDEC Publication 95, MO-153
aaa C
10-0039
Ordering Information
Vendor P/N
ICS9LPRS365yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device
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ICS9LPRS365
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THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS SYMBOL A A1 A3 b e
DIMENSIONS MIN. MAX. 0.8 1.0 0 0.05 0.25 Reference 0.18 0.3 0.50 BASIC SYMBOL N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. ICS 64L TOLERANCE 64 16 16 9.00 x 9.00 7.00 / 7.25 7.00 / 7.25 0.30 /0 .50
Ordering Information
ICS9LPRS365yKLFT
Example:
ICS XXXX y K LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device
1218--07/11/06
26
Integrated
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ICS9LPRS365
Advance Information
Systems, Inc.
Revision History
Rev. 0.1 0.2 Issue Date 4/5/2006 7/11/2006 Description Initial Release Updated Electrical Characteristics. Page # 12
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